1. Field of the Invention
The present invention relates to a multiplexing apparatus for multiplexing plural input data (digital signals) of 400 BPS to 9600 BPS, for example, and plural data of 1.544 MBPS to plural data of 1.544 MBPS.
2. Description of the Prior Art
FIG. 1 is a schematic diagram for showing a configuration of an internal arrangement of the conventional type of multiplexing apparatus disclosed in Japanese patent Laid-Open No 61-163741 submitted with the Japanese Patent Office. Reference numerals wherein 1a-1n denote low-speed circuits, and each of these circuits is connected to each of terminal cards 2a to 2n. Reference numeral 3 designates an input bus and reference numeral 4 denotes an output bus. These are connected in common to the terminal cards 2a to 2n.
Reference numeral 5a denotes a high-speed circuit card; reference numeral 5b denotes a second high-speed card; and reference numeral 7 designates a timing control circuit and each of them is connected to the input bus 3 and the output bus 4, respectively
Reference numeral 6a denotes a first high-speed circuit and reference numeral 6b designates a second high-speed circuit. Each of the high-speed circuits is connected to the high-speed circuit card 5a and the second high-speed circuit card 5b.
To the timing control circuit 7 is connected an address bus 8. The timing control circuit 7 also outputs a synchronous clock signal 9. The address bus 8 is connected to the terminal cards 2a to 2n and the synchronous clock 9 is connected to the first high-speed circuit card 5a and the second high-speed circuit card 5b. Within the second high-speed circuit card 5b are a shift register 10 and a selector 11: and to the shift register 10 receives the synchronous clock 9 and is connected to the selector 11.
In FIG. 3, reference numeral 13 denotes data on either an input bus or output bus. Reference numeral 14 denotes a synchronous clock signal 9. Reference numeral 15 denotes the synchronous clock signal 9 after shifting; Reference numeral 16 designates data on the first high-speed circuit. Reference numeral 17 denotes data on the second high-speed circuit.
Next, the operation of this device will be described. FIG. 2 illustrates a standard configuration of a PCM (Pulse Code Modulation) signal. A configuration of bits consists of a synchronous bit of one bit and data bits of 192 bits and one frame is constructed by these bits In this embodiment, one bit of 192 bits is used to cause the synchronous bit to have a value of 2. If a symbol showing one cycle in 20 frames is applied to the synchronous bit, a period for every 20 frames can be detected. Since one frame is of 125 .mu.sec, one multi-frame occupies 2.5 msec. Accordingly, since one bit on one multi-frame is one bit per 2.5 msec, information using 400 BPS can be transferred. Thus, if n bits in one multi-frame are assigned for a transmittance of 400*nBPS, data ranging from a low-speed to a high-speed can be directly multiplexed. One multi-frame contains data of 193*20=3860 bits.
Then, in FIG. 1, the timing control circuit 7 has a counter cyclically operating at a period of 3860 and transmits a synchronous clock signal 9 once per 3860 times. The timing control circuit 7 has memories corresponding to the addresses of the terminal cards 2a to 2n for every counter values of 3860 pieces. The addresses outputted from the memories are transmitted to each of the terminal cards 2a to 2n through the address bus 8. The address values are compared with an address value of each of the cards by an address decoder in the terminal cards 2a to 2n. Subsequently, the terminal cards 2a to 2n can then use the input bus 3 and the output bus 4 only when a specified terminal card is selected
The first and second high-speed circuit cards 5a and 5b may detect at first a synchronizing bit from the bits inputted from the first and second high-speed circuits 6a and 6b and fetch the input data. The first high-speed circuit card 5a may transmit the input data to the input bus 3 in compliance with a synchronizing clock signal sent from the timing control circuit 7. Since all the data sent from the first high-speed circuit 6a are determined in advance for their bits to be assigned to what terminal, a length of data representing their sum is already known. Thus the value of the selector 11 in the second high-speed circuit card 5b is set to be delayed by an amount corresponding to this data length. Since the second high-speed circuit card 5b may transmit the input data to the input bus 3 in synchronous with the shifted synchronous clock signal 15, the data from the first high-speed circuit 6a is not overlapped with the data from the second high-speed circuit 6b on the input bus 3 as indicated in the data on the input or output bus 13.
As shown in data 16 in the first high-speed circuit, the output is made such that the first high-speed circuit card 5a may provide a synchronous bit in compliance with the synchronous clock 14 to transmit the data on the output bus 4 to the high-speed circuit 6a. As shown by the data on the second high-speed circuit 17, the second high-speed circuit card 5b may provide a synchronous bit in compliance with the shifted synchronous clock 15 and transmit the data of the output bus 4 to the high-speed circuit 6b.
Since the conventional type of multiplexing apparatus is constructed as described above, it had a problem that data could not be transmitted from one high-speed circuit to the other high-speed circuit through a multiplexing device.